The present invention generally relates to a metal insulator semiconductor type memory device, and particularly to a metal insulator semiconductor type dynamic random access memory device having stacked capacitor type memory cells. More particularly, the present invention relates to improvement in the structure and layout (arrangement) of memory cells.
A one-transistor one-capacitor type memory cell is widely used as a memory cell of a metal insulator semiconductor type dynamic random access memory (hereafter simply referred to as a MIS type DRAM or just DRAM). Currently, a 1-Mbit DRAM and a 4-Mbit DRAM are available. It is required to reduce the cell size per one bit to achieve the integration density equal to or more than 1 Mbits. A trench type memory cell and a stacked capacitor type memory cell have been proposed in order to reduce the cell size per one bit. A trench type memory cell is a cell in which a capacitor, which is a structural element of a memory cell, is formed in a silicon substrate. A stacked capacitor type memory cell is a cell in which a capacitor is formed above a silicon substrate.
Referring to FIG. 1, there is illustrated the structure of a conventional DRAM. The illustrated DRAM includes a memory cell array 1, which is made up of a plurality of memory cells arranged in a matrix form. The DRAM includes an address buffer 2, a row decoder 3, a column decoder 4, a sense amplifier 5, and a data output buffer 6. Those elements form peripheral circuits of the memory cell array 1. In the illustrated DRAM, it is not reasonable that we try to enhance the integration density of the illustrated DRAM at the sacrifice of electrical characteristics of memory cells. Similarly, it is not reasonable that we try to improve electrical characteristics of memory cells at the sacrifice of the integration density. This means that we should research and develop DRAM devices by taking account of not only the memory cell array 1 but also the peripheral circuits such as the row decoder 3, column decoder 4 and the sense amplifier 5.
FIGS. 2A and 2B illustrate equivalent circuits each showing the connection between the sense amplifier 5 and the memory cell array 1. FIG. 2A relates to the folded bit line type, and FIG. 2B relates to the open bit line type. In FIGS. 2A and 2B, MC is a memory cell formed in the memory cell array 1, and S/A is a sense amplifier which is formed in the sense amplifier 5 and
is provided for each of pairs of bit lines BL and BL. As shown, bit lines BL (BL) and word lines WL in conventional MIS type DRAMs are arranged so as to form a mesh. One memory cell MC is provided at an intersection of one bit line BL (BL) and one word line WL. The folded bit line type DRAM has a pair of bit lines BL and BL which are folded at one related sense amplifier S/A and extend in parallel. The open bit line type DRAM has a pair of bit lines BL and BL which extend in opposite directions from one related sense amplifier S/A.
Generally, the sense amplifier S/A includes two transistors forming a flip-flop with respect to a pair of bit lines BL and BL. On the other hand, the row decoder 3 includes one transistor for one word line WL. Therefore, the size of the sense amplifier 5 is necessarily large than the size of the row decoder 3, and thus the design of the sense amplifier 5 is complicated. The bit line pitch (the distance between adjacent bit lines) must match the sense amplifier pitch, with which the sense amplifiers S/A are arranged. Such matching is achieved in the folded bit line type with ease, as compared with the open bit line type. This will be seen from FIG. 2A. That is, one sense amplifier S/A is arranged in the distance between the bit lines BL1 and BL2 (BL1 and BL2).
On the other hand, in the open bit line type, one sense amplifier S/A must be positioned within one pitch of bit lines. Therefore, it becomes difficult to form one sense amplifier S/A within one pitch of bit lines as the size of the memory cells MC are reduced. This means that the bit line pitch must be selected based on the size of the sense amplifiers S/A. In other words, the size of DRAM devices greatly depends on the size of the sense amplifiers S/A (not the size of memory cells MC). If it becomes possible to match the sense amplifier pitch and the bit line pitch without increasing the entire size of the memory cell array 1, an increased integration density can be obtained. This also provide a higher freedom in design of peripheral circuits.
The inventor knows some proposals for overcoming the above-mentioned problems. For example, the following paper discloses an improved open bit line type memory cell configuration: M. Koyanagi et al. "Novel High Density Stacked Capacitor MOS RAM", Japn. J. Appl. Phys. Vol. 18 (1979), Supplement 18-1, PP. 35-42. FIG. 3A is a plan view of a memory cell configuration disclosed in the above-mentioned paper, and FIG. 3B is an elevational view taken along the lines 3B--3B in FIG. 3A. The memory cell includes sources 201, drains 202, storage electrodes 203, opposed electrodes 204, insulating (dielectric) films 205, contact holes 206, bit lines 211, and word lines 212. The illustrated structure employs the stacked capacitor type memory cells. Although the proposed structure provides a field effect transistor (FET) of a reduced size, it is too small to match the sense amplifier pitch and the bit line pitch. In other words, the element density of a memory device greatly depends on the size of the sense amplifiers, as compared with the size of the memory cells.
Another improvement has been proposed in Japanese Laid-Open Patent Application No. 61-183955. This proposal intends to enhance the integration density by providing the arrangement (layout) of peripheral circuits with an improvement. In the proposal, bit lines extending in opposite directions from a sense amplifier are arranged in an interdigital arrangement. With this arrangement, the sense amplifier pitch is doubled. However, an increased density of memory cells is not expected.
Generally, it is desired that the capacitance value of a capacitor of a memory cell is as large as possible. This is because a large cell capacitance stabilizes the operation of a memory cell and provides increased immunity to soft errors. For these reasons, it is desired to efficiently and effectively utilize an area assigned to a memory cell. However, in the configuration of FIG. 3B, bit lines 211 are formed after forming storage electrodes 203. This makes it difficult to efficiently and effectively utilize the area assigned to memory cells.